This invention relates to a processor for accomplishing bypass control of operands and determination-awaiting control of operands in a data processing (DP) system.
A conventional processor having pipeline-controlled execution stages has a fixed number of operational stages. Accordingly, in some types of operation, the result of the operation may be determined at a stage prior to the final operation stage. However, since the number of stages of the processing pipe is fixed, there is a disadvantage that the earlier determined result of operation cannot be used as the operand of the next operation until the final operation stage.
Meanwhile, there is proposed in U.S. Pat. No. 4,476,525 filed by the same assignee on Aug. 14, 1981, a system by which the write-in stage of an operational instruction is overlapped with that of the following storage instruction so that the time taken for the execution of the following storage instruction can be virtually reduced to "0".
This system, however, has a disadvantage that where an operational instruction and a storage instruction are combined and the two instructions are consecutive, a processor whose processing pipes have multiple stages can have no substantial advantage.